Weebit Matrix brings ReRAM-based in-memory AI research to real silicon
Weebit Nano’s Matrix research program gives academic and industry teams a ReRAM crossbar array, development board and documentation for testing in-memory computing on real silicon.

AT A GLANCE
Key points
- The program provides real ReRAM chips and a development board.
- The 32×32 array supports MAC and vector-matrix operations.
- Access is available to qualified researchers for prototyping.
What is changing?
On November 4, Weebit Nano launched the Matrix In-Memory Compute Research Program. Available to qualified academic and industry researchers, each package includes chips, documentation and a development board with a socket. It is intended for prototyping workloads such as AI inference and neuromorphic computing on real ReRAM hardware.
The Matrix chip uses a 32×32 crossbar array to support multiply-accumulate operations, vector-matrix multiplication, convolution and spiking neural-network experiments. Applications are evaluated against the program’s research focus; the platform is for research and prototyping and does not grant commercial-use rights.
Weebit says in-memory computing could reduce data movement between processors and memory. Its power and latency claims still require independent validation, and the official announcement acknowledges that technical challenges remain before a commercial IMC product.
Explore the original sources
Source date: 4 November 2026.
Published by AI Radar: 4 Nov 2026, 23:05 (Istanbul, UTC+3).
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